Information for file /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/DLS_1ton.DLS_1ton.core.cpp
| Name | /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/DLS_1ton.DLS_1ton.core.cpp |
|---|---|
| Digest (sha256) | bc6f1c06abdd7eaa10930caf109461dd6d1239398865c5ccd1264f03030c4a43 |
| Size | 17.14 KB |
| Modification time | Sun, 06 Nov 2022 10:48:34 UTC |
| User | root |
| Group | root |
| Mode | -rw-r--r-- |
| Flags | |
| RPM | qucs-debugsource-0.0.20~rc2-2.fc37.riscv64.rpm |
