Information for file /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/comp_1bit.core.h
| Name | /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/comp_1bit.core.h |
|---|---|
| Digest (sha256) | c498fd71c7ef3088cb5bccce29e588bc7a48d9607c84c591e8edd46953a6a598 |
| Size | 1.61 KB |
| Modification time | Sun, 06 Nov 2022 10:50:32 UTC |
| User | root |
| Group | root |
| Mode | -rw-r--r-- |
| Flags | |
| RPM | qucs-debugsource-0.0.20~rc2-2.fc37.riscv64.rpm |
