Information for file /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/logic_0.core.h
| Name | /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/logic_0.core.h |
|---|---|
| Digest (sha256) | 5d985b333714e4a5452fa3cc404d52383f9004a7ec2570484ddf0c24265938cf |
| Size | 1.54 KB |
| Modification time | Sun, 06 Nov 2022 10:47:50 UTC |
| User | root |
| Group | root |
| Mode | -rw-r--r-- |
| Flags | |
| RPM | qucs-debugsource-0.0.20~rc2-2.fc37.riscv64.rpm |
