Information for file /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/logic_1.core.h
| Name | /usr/src/debug/qucs-0.0.20~rc2-2.fc37.riscv64/qucs-core/src/components/verilog/logic_1.core.h |
|---|---|
| Digest (sha256) | f5c8bfbbaedf25724b1a8fb1a6c22eea8078cdba1273a2fa592e2e9cfe2ccff3 |
| Size | 1.54 KB |
| Modification time | Sun, 06 Nov 2022 10:47:57 UTC |
| User | root |
| Group | root |
| Mode | -rw-r--r-- |
| Flags | |
| RPM | qucs-debugsource-0.0.20~rc2-2.fc37.riscv64.rpm |
