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Information for RPM iverilog-12.0-2.fc40.riscv64.rpm

ID1140710
Nameiverilog
Version12.0
Release2.fc40
Epoch
Archriscv64
SummaryIcarus Verilog is a verilog compiler and simulator
DescriptionIcarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
Build Time2023-12-08 02:28:32 GMT
Size2.29 MB
34dc2c4d7d09f6ad24222a35126ade27
LicenseGPLv2
Buildrootf40-build-757405-119337
Provides
iverilog = 12.0-2.fc40
iverilog(riscv-64) = 12.0-2.fc40
Obsoletes No Obsoletes
Conflicts No Conflicts
Requires
/usr/bin/sh
ld-linux-riscv64-lp64d.so.1()(64bit)
ld-linux-riscv64-lp64d.so.1(GLIBC_2.27)(64bit)
libbz2.so.1()(64bit)
libc.so.6()(64bit)
libc.so.6(GLIBC_2.27)(64bit)
libc.so.6(GLIBC_2.33)(64bit)
libc.so.6(GLIBC_2.34)(64bit)
libc.so.6(GLIBC_2.38)(64bit)
libgcc_s.so.1()(64bit)
libgcc_s.so.1(GCC_3.0)(64bit)
libgcc_s.so.1(GCC_3.4)(64bit)
libm.so.6()(64bit)
libm.so.6(GLIBC_2.27)(64bit)
libreadline.so.8()(64bit)
libstdc++.so.6()(64bit)
libstdc++.so.6(CXXABI_1.3)(64bit)
libstdc++.so.6(CXXABI_1.3.8)(64bit)
libstdc++.so.6(GLIBCXX_3.4)(64bit)
libstdc++.so.6(GLIBCXX_3.4.11)(64bit)
libstdc++.so.6(GLIBCXX_3.4.15)(64bit)
libstdc++.so.6(GLIBCXX_3.4.20)(64bit)
libstdc++.so.6(GLIBCXX_3.4.21)(64bit)
libstdc++.so.6(GLIBCXX_3.4.29)(64bit)
libstdc++.so.6(GLIBCXX_3.4.30)(64bit)
libstdc++.so.6(GLIBCXX_3.4.32)(64bit)
libstdc++.so.6(GLIBCXX_3.4.9)(64bit)
libz.so.1()(64bit)
libz.so.1(ZLIB_1.2.0)(64bit)
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
rpmlib(PayloadFilesHavePrefix) <= 4.0-1
rpmlib(PayloadIsZstd) <= 5.4.18-1
rtld(GNU_HASH)
Recommends No Recommends
Suggests No Suggests
Supplements No Supplements
Enhances No Enhances
Files
Page:
1 through 50 of 127 >>>
Name Size descending sort
/usr/lib64/ivl/ivl2.64 MB
/usr/bin/vvp1.31 MB
/usr/lib64/ivl/vhdlpp533.93 KB
/usr/lib64/ivl/system.vpi416.02 KB
/usr/lib64/libveriuser.a298.27 KB
/usr/lib64/ivl/vhdl.tgt285.65 KB
/usr/lib64/ivl/vvp.tgt183.27 KB
/usr/lib64/ivl/vlog95.tgt154.59 KB
/usr/include/ivl_target.h94.29 KB
/usr/lib64/ivl/stub.tgt77.45 KB
/usr/lib64/ivl/pcb.tgt69.16 KB
/usr/lib64/ivl/ivlpp68.80 KB
/usr/lib64/ivl/cadpli.vpl53.31 KB
/usr/bin/iverilog52.84 KB
/usr/lib64/ivl/blif.tgt48.41 KB
/usr/share/doc/iverilog/examples/des.v46.81 KB
/usr/lib64/ivl/v2009.vpi40.02 KB
/usr/lib64/ivl/sizer.tgt32.02 KB
/usr/lib64/ivl/vhdl_textio.vpi32.01 KB
/usr/lib64/ivl/vhdl_sys.vpi27.70 KB
/usr/include/vpi_user.h24.30 KB
/usr/lib64/ivl/v2005_math.vpi19.84 KB
/usr/share/doc/iverilog/ieee1364-notes.txt19.38 KB
/usr/share/licenses/iverilog/COPYING17.67 KB
/usr/lib64/ivl/va_math.vpi15.48 KB
/usr/lib64/ivl/vpi_debug.vpi15.20 KB
/usr/lib64/ivl/null.tgt14.98 KB
/usr/share/doc/iverilog/netlist.txt13.33 KB
/usr/share/doc/iverilog/examples/sqrt-virtex.v11.76 KB
/usr/include/veriuser.h11.45 KB
/usr/share/man/man1/iverilog.1.gz8.99 KB
/usr/share/doc/iverilog/BUGS.txt7.50 KB
/usr/include/acc_user.h7.48 KB
/usr/share/doc/iverilog/fpga.txt6.17 KB
/usr/share/doc/iverilog/examples/pal_reg.v4.27 KB
/usr/share/doc/iverilog/examples/sqrt.vl3.93 KB
/usr/share/doc/iverilog/examples/show_vcd.vl3.82 KB
/usr/bin/iverilog-vpi3.79 KB
/usr/share/doc/iverilog/xilinx-hint.txt3.74 KB
/usr/share/doc/iverilog/va_math.txt3.72 KB
/usr/share/doc/iverilog/examples/xnf_add.vl3.65 KB
/usr/share/doc/iverilog/examples/clbff.v3.30 KB
/usr/share/man/man1/vvp.1.gz3.18 KB
/usr/share/doc/iverilog/extensions.txt3.02 KB
/usr/share/doc/iverilog/QUICK_START.txt2.95 KB
/usr/share/doc/iverilog/attributes.txt2.84 KB
/usr/share/doc/iverilog/examples/outff.v2.76 KB
/usr/include/sv_vpi_user.h2.55 KB
/usr/include/_pli_types.h2.45 KB
/usr/share/doc/iverilog/swift.txt2.34 KB
Component of
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Buildroot descending sort Created State
f40-build-769274-125504 2023-12-31 09:01:36 expired