Thu, 13 Jun 2024 07:18:04 UTC | login

Information for RPM iverilog-11.0-6.fc37.riscv64.rpm

ID875376
Nameiverilog
Version11.0
Release6.fc37
Epoch
Archriscv64
SummaryIcarus Verilog is a verilog compiler and simulator
DescriptionIcarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
Build Time2022-11-08 15:45:21 GMT
Size2.09 MB
0d51a71574971607b50005d6921600a3
LicenseGPLv2
Buildrootf37-build-668840-74806
Provides
iverilog = 11.0-6.fc37
iverilog(riscv-64) = 11.0-6.fc37
Obsoletes No Obsoletes
Conflicts No Conflicts
Requires
/usr/bin/sh
ld-linux-riscv64-lp64d.so.1()(64bit)
ld-linux-riscv64-lp64d.so.1(GLIBC_2.27)(64bit)
libbz2.so.1()(64bit)
libc.so.6()(64bit)
libc.so.6(GLIBC_2.27)(64bit)
libc.so.6(GLIBC_2.33)(64bit)
libc.so.6(GLIBC_2.34)(64bit)
libgcc_s.so.1()(64bit)
libgcc_s.so.1(GCC_3.0)(64bit)
libgcc_s.so.1(GCC_3.3.1)(64bit)
libgcc_s.so.1(GCC_3.4)(64bit)
libm.so.6()(64bit)
libm.so.6(GLIBC_2.27)(64bit)
libreadline.so.8()(64bit)
libstdc++.so.6()(64bit)
libstdc++.so.6(CXXABI_1.3)(64bit)
libstdc++.so.6(CXXABI_1.3.8)(64bit)
libstdc++.so.6(CXXABI_1.3.9)(64bit)
libstdc++.so.6(GLIBCXX_3.4)(64bit)
libstdc++.so.6(GLIBCXX_3.4.11)(64bit)
libstdc++.so.6(GLIBCXX_3.4.15)(64bit)
libstdc++.so.6(GLIBCXX_3.4.20)(64bit)
libstdc++.so.6(GLIBCXX_3.4.21)(64bit)
libstdc++.so.6(GLIBCXX_3.4.26)(64bit)
libstdc++.so.6(GLIBCXX_3.4.29)(64bit)
libstdc++.so.6(GLIBCXX_3.4.30)(64bit)
libstdc++.so.6(GLIBCXX_3.4.9)(64bit)
libz.so.1()(64bit)
libz.so.1(ZLIB_1.2.0)(64bit)
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
rpmlib(PayloadFilesHavePrefix) <= 4.0-1
rpmlib(PayloadIsZstd) <= 5.4.18-1
rtld(GNU_HASH)
Recommends No Recommends
Suggests No Suggests
Supplements No Supplements
Enhances No Enhances
Files
Page:
<<< 51 through 100 of 128 >>>
Name Size ascending sort
/usr/lib64/ivl/stub.conf49.00 B
/usr/lib64/ivl/vlog95.conf57.00 B
/usr/lib64/ivl/null-s.conf65.00 B
/usr/lib64/ivl/vvp.conf81.00 B
/usr/lib64/ivl/vhdl.conf86.00 B
/usr/lib64/ivl/pcb-s.conf95.00 B
/usr/lib64/ivl/blif-s.conf96.00 B
/usr/lib64/ivl/blif.conf96.00 B
/usr/lib64/ivl/stub-s.conf96.00 B
/usr/lib64/ivl/sizer-s.conf97.00 B
/usr/lib64/ivl/sizer.conf97.00 B
/usr/lib64/ivl/vhdl-s.conf103.00 B
/usr/lib64/ivl/vvp-s.conf128.00 B
/usr/lib64/ivl/vlog95-s.conf141.00 B
/usr/share/doc/iverilog/mingw.txt237.00 B
/usr/lib64/ivl/include/disciplines.vams1.10 KB
/usr/share/doc/iverilog/glossary.txt1.29 KB
/usr/lib64/ivl/include/constants.vams1.34 KB
/usr/share/doc/iverilog/examples/xram16x1.v1.41 KB
/usr/share/doc/iverilog/examples/hello.vl1.60 KB
/usr/share/man/man1/iverilog-vpi.1.gz1.61 KB
/usr/share/doc/iverilog/cadpli.txt1.63 KB
/usr/share/doc/iverilog/examples/hello_vpi.vl1.63 KB
/usr/share/doc/iverilog/examples/hello_vpi.c1.77 KB
/usr/share/doc/iverilog/vpi.txt2.04 KB
/usr/share/doc/iverilog/t-dll.txt2.05 KB
/usr/include/sv_vpi_user.h2.32 KB
/usr/share/doc/iverilog/swift.txt2.34 KB
/usr/include/_pli_types.h2.45 KB
/usr/share/doc/iverilog/examples/outff.v2.76 KB
/usr/share/doc/iverilog/attributes.txt2.84 KB
/usr/share/doc/iverilog/QUICK_START.txt2.95 KB
/usr/share/doc/iverilog/extensions.txt3.02 KB
/usr/share/man/man1/vvp.1.gz3.17 KB
/usr/share/doc/iverilog/examples/clbff.v3.30 KB
/usr/share/doc/iverilog/examples/xnf_add.vl3.65 KB
/usr/share/doc/iverilog/va_math.txt3.72 KB
/usr/share/doc/iverilog/xilinx-hint.txt3.74 KB
/usr/bin/iverilog-vpi3.75 KB
/usr/share/doc/iverilog/examples/show_vcd.vl3.82 KB
/usr/share/doc/iverilog/examples/sqrt.vl3.93 KB
/usr/share/doc/iverilog/examples/pal_reg.v4.27 KB
/usr/lib64/libvpi.a6.11 KB
/usr/share/doc/iverilog/fpga.txt6.17 KB
/usr/include/acc_user.h7.48 KB
/usr/share/doc/iverilog/BUGS.txt7.50 KB
/usr/share/man/man1/iverilog.1.gz8.95 KB
/usr/include/veriuser.h11.45 KB
/usr/share/doc/iverilog/examples/sqrt-virtex.v11.76 KB
/usr/share/doc/iverilog/netlist.txt13.33 KB
Component of
1 through 2 of 2
Buildroot descending sort Created State
f37-build-678625-76382 2022-11-15 21:37:18 expired
f37-build-673823-75679 2022-11-12 00:57:30 expired