Sequential logic synthesis and formal verification
Description
ABC is a growing software system for synthesis and verification of
binary sequential logic circuits appearing in synchronous hardware
designs. ABC combines scalable logic optimization based on And-Inverter
Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up
tables and standard cells, and innovative algorithms for sequential
synthesis and verification.
ABC provides an experimental implementation of these algorithms and a
programming environment for building similar applications. Future
development will focus on improving the algorithms and making most of
the packages stand-alone. This will allow the user to customize ABC for
their needs as if it were a toolbox rather than a complete tool.
Build Time
2024-09-26 16:30:26 GMT
Size
5.98 MB
e8dc329f69bf6a7d97f944c9647b2f73
License
MIT-Modern-Variant AND MIT AND BSD-2-Clause AND BSD-3-Clause
