Open Verification Methodology : IEEE 1800 SystemVerilog standard
Description
The OVM is based on the IEEE 1800 SystemVerilog standard and supports design
and verification engineers developing advanced verification environments that
offer higher levels of integration and portability of Verification IP. The
methodology is non-vendor specific and is interoperable with multiple languages
and simulators. The OVM is fully open, and includes a robust class library and
source code that is available for download.
