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Information for RPM verilator-3.922-2.fc29.src.rpm

ID228220
Nameverilator
Version3.922
Release2.fc29
Epoch
Archsrc
SummaryA fast simulator for synthesizable Verilog
DescriptionVerilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
Build Time2018-08-07 22:25:15 GMT
Size2.07 MB
3904be5f796ff173f64b05f98d576b67
LicenseLGPLv3 or Artistic 2.0
Buildrootf29-build-23630-12081
Provides No Provides
Obsoletes No Obsoletes
Conflicts No Conflicts
Requires
bison
coreutils
findutils
flex
gcc
gcc-c++
perl(Data::Dumper)
perl(Getopt::Long)
perl(IO::File)
perl(Pod::Usage)
perl(strict)
perl(vars)
perl-generators
perl-interpreter
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
sed
Recommends No Recommends
Suggests No Suggests
Supplements No Supplements
Enhances No Enhances
Files
1 through 2 of 2
Name ascending sort Size
verilator-3.922.tgz2.06 MB
verilator.spec7.91 KB
Component of No Buildroots